1. Field of the Invention
The present invention relates to a charge-coupled device (CCD) and a CCD solid state imaging device, such as an area sensor, a linear sensor or the like.
2. Description of the Prior Art
Heretofore, CCD solid state imaging devices, such as an area sensor, a linear sensor or the like, include an overflow mechanism to discharge excess electric charges produced when a sensor section thereof senses a large quantity of light. As such an overflow mechanism, there is known an overflow mechanism which includes an overflow control gate section and an overflow drain region provided in the lateral direction to thereby adjust an overflow level by a gate voltage from the overflow control gate section, or a mechanism in which an overflow level is set by a potential barrier without using the gate voltage.
A CCD solid state imaging device having such an overflow mechanism, i.e., a linear sensor, will be described below.
FIG. 1 of the accompanying drawings shows an example of a conventional linear sensor having an overflow control gate section. As shown in FIG. 1, a linear sensor 1 is comprised of a sensor array 3 in which a plurality of sensor sections (photo-sensing sections) 2 are arranged in a one-dimensional fashion in the horizontal direction, a horizontal transfer register 5 having a CCD structure provided on one side of the sensor array through a read-out gate section 4, an overflow control gate section 6 provided adjacent to the other side of the sensor array 3 to determine an overflow level and an overflow drain region 7 for discharging excess electric charges. Furthermore, the linear sensor 1 includes an output section 8 connected to the final stage of the horizontal transfer register 5, and the output section 8 includes a charge-to-voltage converting section for converting a signal charge transferred thereto from the horizontal transfer register 5 into a voltage.
FIG. 2 is a cross-sectional view taken along the line II--II in FIG. 1. As shown in FIG. 2, in this linear sensor 1, an N-type impurity diffusion region 12 is formed on a P-type well region 11 and a P-type positive charge accumulation region 13 is formed on the surface of the N-type impurity diffusion region 12, and the sensor section (photoelectric conversion section) 2 is formed by a PN junction photo-diode provided therein. The overflow drain region 7 is formed by an N-type impurity diffusion layer. The overflow drain region 7 and the sensor section 2 have the overflow control gate section 6 therebetween having a gate electrode 14 to which a predetermined gate voltage V.sub.OFCG is applied through a gate insulating film.
The horizontal transfer register 5 includes a plurality of transfer sections 16 having a storage gate electrode 15s formed of a first polycrystalline silicon layer and a transfer gate electrode 15t formed of a second polycrystalline silicon layer along a charge transfer direction a. The horizontal transfer register 5 is driven by two-phase clock pulses .phi.H.sub.1 and .phi.H.sub.2. The read-out gate section 4 includes a read-out gate electrode 17 to which a read-out gate pulse .phi.ROG is applied through the gate insulating film. The read-out gate section 4 is connected to a transfer section having the transfer gate electrode 15t of the horizontal transfer register 5.
In the linear sensor 1, signal charges photoelectrically-converted by each sensor section 2 are read out through the read-out gate section 4 to the horizontal transfer register 5, transferred within the horizontal transfer register 5 in the arrow a direction, photoelectrically-converted and then sequentially outputted through an output section 8.
The overflow control gate section 6 fixes a potential (i.e., potential barrier) V.sub.ofb1 when applied with the predetermined gate voltage V.sub.OFCG as shown in FIGS. 2A, 2B. A maximum amount of electric charges handled by the sensor section 2 is determined by a barrier height .DELTA.V.sub.b1 provided between the potential V.sub.ofb1 and a potential Vs formed under the sensor section 2. If many electric charges are generated by the sensor section 2 when the sensor section 2 senses a large quantity of light, excess electric charges are discharged to the overflow drain region 7 through the potential barrier V.sub.ofb1 formed under the overflow control gate section 6.
FIG. 3 and FIGS. 4A, 4B show another example of a conventional linear sensor having an overflow barrier region. In FIG. 3 and FIGS. 4A, 4B, like parts corresponding to those of FIG. 1 and FIGS. 2A, 2B are marked with the same references and therefore need not be described in detail.
As illustrated, a linear sensor 19 is comprised of the sensor array 3 formed of a plurality of sensor sections 2, the horizontal transfer register 5 having the CCD structure provided at one side of the sensor array 3 through the read-out gate section 4, the output section 8 connected to the final stage of the horizontal transfer register 5, an overflow barrier region 18 provided adjacent to the other side of the sensor array 3 to determine an overflow level and the overflow drain region 17 for discharging excess electric charges.
FIG. 4A is a cross-sectional view taken along the line IV--IV in FIG. 3. As shown in FIG. 4A, the overflow barrier region 18 includes an N.sup.- type impurity diffusion region 20 having a donor concentration lower than that of the N-type impurity diffusion region 12 forming the sensor section 2 formed under an extended section 13a of a P-type positive electric charge accumulation region 13. The N-type impurity diffusion region 20 forms a potential (i.e., potential barrier) V.sub.ofb2 which is shallower than the potential Vs of the sensor section 2, and a maximum amount of electric charges handled by the sensor section 2 is determined by a barrier height .DELTA.V.sub.b2. Structures of the sensor section 2, the horizontal transfer register 5, the overflow drain region 7, etc., are similar to those of FIG. 2A.
In this linear sensor, when many electric charges are generated from the sensor section 2, the excess electric charges are discharged to the overflow drain region 7 through the potential barrier V.sub.ofb2 formed under the overflow barrier region 18.
In the case of the former linear sensor 1, as shown in FIGS. 2A, 2B, the potential V.sub.ofb1 formed under the overflow control gate section 6 is substantially fixed by the gate voltage V.sub.OFCG. Therefore, while the fluctuation of the barrier height .DELTA.V.sub.b1 is small when the potential of the overflow drain region 7 is fluctuated (see a broken line in FIG. 2B), if the potential Vs of the sensor section 2 is deviated (see a one-dot chain line in FIG. 2B) from a design value, then the barrier height V.sub.b1 is changed and a so-called overflow level is changed. A curve I in FIG. 5 shows a relationship between an exposure amount and an amount of signal charges thus read-out. Accordingly, this linear sensor 1 should adjust the gate voltages of the overflow control gate section 6 separately in response to the deviated amount of the potential Vs of the sensor section 2 from the design value. Thus, the linear sensor 1 cannot provide a stable overflow characteristic without substantially adjustment.
In the case of the latter linear sensor 19, as shown in FIGS. 4A, 4B, the fluctuation of the potential V.sub.ofb2 of the overflow barrier region 18 is small when the potential Vs of the sensor section 2 is fluctuated (see a one-dot chain line in FIG. 4B). However, when the voltage of the overflow drain region 7 is fluctuated (see a broken line in FIG. 4B), the potential V.sub.ofb2 formed under the overflow barrier region 18 is modulated (shown by the broken line in FIG. 4B) so that the barrier height .DELTA.V.sub.b2 is changed. Therefore, the linear sensor 19 cannot stabilize an overflow characteristic without adjustment.
The conventional overflow drain structure which discharges excess electric charges will be described further. A vertical type overflow drain structure or a horizontal type overflow drain structure in practice will now be described.
FIG. 6 shows a conventional CCD solid state imaging device 21 which comprises linear sensors arrayed in a plurality of lines and vertical transfer registers added thereto.
As shown in FIG. 6, the CCD solid state imaging device 21 includes linear sensors 26 formed of sensor arrays 23 in which a plurality of sensor sections (photo-sensing sections) 22 are arranged in a one-dimensional fashion in the horizontal direction, horizontal transfer registers 24 having a CCD structure provided on one side of the sensor arrays 23 and read-out gate sections 25 provided between the sensor arrays 23 and the horizontal transfer registers 24. In this case, the linear sensors 26 are provided in a plurality of lines, in this example, 3 lines in the vertical direction. A vertical transfer register 27 having a CCD structure is provided at the end of the charge transfer direction of the horizontal transfer registers 24 (24A, 24B, 24C) of respective lines. Further, an output section 28 is connected to the final stage of the vertical transfer register 27, and the output section 28 includes a charge-to-voltage converting unit for converting signal charges transferred within the vertical transfer register 27 into voltages.
Though not shown, the CCD solid state imaging device 21 includes a vertical or horizontal overflow mechanism. When the sensor section 22 photo-senses a large quantity of light, excess charges are discharged to the vertical or horizontal overflow mechanism.
Common two-phase clock pulses .phi.H.sub.1 and .phi.H.sub.2 are applied to the horizontal transfer registers 24 (24A, 24B, 24C) of respective lines. A common read-out gate pulse .phi.ROG is applied to the read-out gate section 25, and drive pulses, i.e., two-phase clock pulses .phi.V.sub.1 and .phi.V.sub.2, are applied to the vertical transfer register 27.
FIG. 7 is a diagram showing a transfer section for transferring signal charges from the horizontal transfer register 24 to the vertical transfer register 27 in an enlarged scale. In the horizontal transfer register 24, a transfer section 33 is comprised of a storage section 32S having a storage gate electrode 33S formed of a first polycrystalline silicon layer and a transfer section 32T having a transfer gate electrode 31T formed of a second polycrystalline silicon layer. There are formed a plurality of stages of the transfer sections 33. The storage gate electrodes 31S and the transfer gate electrodes 31T of the respective transfer sections 33 are connected commonly to the two-phase clock pulses .phi.H.sub.1 and .phi.H.sub.2 in alternate fashion.
In the vertical transfer register 27, a transfer section 36 is comprised of a storage section 35S having a storage gate electrode 34S formed of a first polycrystalline silicon layer and a transfer section 35T having a transfer gate electrode 34T formed of a second polycrystalline silicon layer. There are provided a plurality of stages of the transfer sections 36. The storage gate electrodes 34S and the transfer gate electrodes 34T of the transfer sections 36 are connected commonly to the two-phase clock pulses .phi.V.sub.1 and .phi.V.sub.2 in alternate fashion.
The storage section 32S of the transfer section 33 of the final stage of the horizontal transfer register 24 is connected to the transfer section 35T of the predetermined transfer section 36 of the vertical transfer register 27.
A gate electrode 37 of the read-out gate section 25 provided between the sensor section 22 and the horizontal transfer register 24 is formed of a first polycrystalline silicon layer. The read-out gate section 25 is connected to the transfer section 32T of the horizontal transfer register 24. A dashed line 18 in FIG. 7 shows a transfer channel region.
The clock pulses .phi.H.sub.1, .phi.H.sub.2, .phi.V.sub.1, .phi.V.sub.2, .phi.ROG are applied to the CCD solid state imaging device 21 at timings shown in FIG. 8, so that signal charges of the sensor arrays 23 (123A, 23B, 23C) of the respective lines are read out through the read-out gate sections 25 (25A, 25B, 25C) to the corresponding horizontal transfer registers 24 (24A, 24B, 24C). The signal charges supplied thereto are sequentially transferred at every signal charge of one pixel of each line to the vertical transfer register 27. The signal charges transferred to the vertical transfer register 27 are transferred in the vertical direction and then sequentially output through the output section 28.
As the outputs signals there can be obtained an output signal of the left-hand end sensor 22 (D1-1) of the first line, an output signal of the left-hand end sensor 22 (D2-1) of the second line, and an output signal of the left-hand end sensor 22 (D3-1) of the third line, in that order. Output signals will be obtained hereinafter in similar fashion.
In the conventional CCD solid state imaging device, the excess signal charges generated when the sensor section photo-senses a large quantity of light are discharged to the vertical or horizontal overflow mechanism as described above. If, however, excess electric charges which are photoelectrically converted are transferred to the transfer register or if light is leaked to the transfer register (i.e., so-called smear occurs) when signal charges are read out from the sensor section, then electric charges are overflowed in the transfer register to destroy signals of other pixels.
In the case of the CCD solid state imaging device 21 shown in FIGS. 6 and 7, if electric charges are overflowed in an arbitrary transfer section 33 of the horizontal transfer register 24 of a certain line, then electric charges are initially overflowed to the transfer section 33 provided before and after the arbitrary transfer section 33 to destroy a signal of that line. If electric charges are overflowed in a larger scale, then electric charges are overflowed in the vertical transfer register 27 so that signals of all pixels are destroyed.
Therefore, if a very large quantity of light is radiated on a certain small portion, there is then the possibility that signals of all pixels are destroyed. This is also true in the case that, even though the CCD solid state imaging device includes the overflow mechanism (so-called vertical or horizontal overflow mechanism, etc.) suppress electric charges from being overflowed in the simple sensor section, if a large amount of photoelectrically-converted electric charges are transferred to the horizontal transfer register when a smear occurs in the horizontal transfer register 24, i.e. a signal is read out, or when the read-out gate is opened.